Test pads are generally provided on a semiconductor chip for testing an LSI. The testing using test pads is intended to detect the presence or absence of failures, such as short circuits among interconnects within a semiconductor chip. The testing may include applying voltages to the test pads and measuring currents generated or measuring a voltage between test pads. The testing is used to ensure required shipping quality.
Japanese Laid-open Patent Publication No. 3-36748 discloses a semiconductor device in which a switching element is provided midway along an interconnect and Japanese Laid-open Patent Publication No. 8-201474 discloses a semiconductor device in which a rectifying element is provided midway along an interconnect. In addition, Japanese Laid-open Patent Publication No. 3-246944 discloses examples of a layout of power supply pads and grounding pads in a semiconductor device and a method for interconnecting these pads.
An increase in the number of circuit blocks including in a semiconductor device results in an increase in the number of power supply lines for supplying power to the respective circuit blocks. Accordingly, the frequency of testing increases in proportion to the number of circuit blocks, thus increasing the amount of time required for conventionally detecting a failure in the semiconductor device.
In addition, as the result of a recent increase in the operating frequency of a semiconductor device and the miniaturization thereof, there is a demand for a reduction in power consumption. As a technique for reducing power consumption, there is a technique in which power supply switches are provided in respective circuit blocks included in a semiconductor device and power to circuits not in use or in low-power-mode is cut off. Hereinafter, this technique is referred to as a power-gating technique.